A 16-bit processor in VHDL

Four-person project for DTU 62711. The system combines a custom datapath, microprogrammed controller, RAM, and a seven-segment interface.

Simulation timing diagram of the port register write path — Simulation timing used to inspect the port-register write path.

The challenge

A display write used the upper byte after an upstream block had forced it to zero. Tracing that path exposed why two digits could never change. Hardware and assembler opcodes also needed to agree.

Results

Programs run in simulation and on the FPGA.
Around 27 VHDL testbenches across the project phases.
Custom Python assembler and a combined project report.

Code, design files & full documentation →